The invention relates to electronic computer memories. Electronic computer memories store data and instructions for use by a central processing unit. For good performance, an electronic computer memory should have a large size, high speed, and low cost.
In order to obtain good performance, it is known to organize electronic computer memories in a memory hierarchy of multiple memory levels. For example, the first memory level (L1) which communicates directly with the central processing unit may comprise a small, high-speed electronic computer memory having a high cost per memory cell. A second memory level (L2), which communicates with the first memory level, but which does not communicate directly with the central processing unit, may comprise a larger, but slower electronic computer memory having a lower cost per memory cell. If desired, a third memory level (L3), which communicates with the second memory level, which optionally communicates with the first memory level, but which does not communicate directly with the central processing unit, may comprise an even larger, but even slower electronic computer memory having an even lower cost per memory cell. Further memory levels may be provided if desired.
The first memory level is generally a set associative cache memory. To obtain high speed, the cache memory contains large sense amplifiers and write drivers which may extend across two or more columns of memory cells (that is, which may extend across two or more bit/sense lines). In a set associative cache memory, access by the central processing unit involves accessing a set of memory cells containing portions of two or more cache blocks, only one of which contains the desired data or instruction. Access from the first memory level to a higher memory level involves accessing an entire single cache block which contains the desired data or instruction.
Designing a set associative cache memory for fast central processing unit access may reduce the access speed to higher memory levels, or may require additional and more costly circuitry to avoid reducing the speed of accessing higher memory levels.